ANALOG VITERBI DECODER

摘要

An analog Viterbi decoder is provided to increase data decoding speed without limit of a sampling speed of a sample and hold circuit. In an analog Viterbi decoder, a decoding unit(10) includes a plurality of processing units consisting of a plurality of cells arranged vertically to correspond to each node of a Trellis diagram, and decodes analog input data by using an analog signal processing cell having a circulation type connection structure that the last unit among the plurality of processing units is connected with the initial unit. An analog data storage unit(20) includes a plurality of condensers connected to the plurality of processing units included in the decoding unit(10) in parallel. An analog signal input unit includes a plurality of sample and hold units(50) in parallel, sampling analog data inputted from the outside and outputting the data, and sequentially alternates each analog data sampled by the plurality of sample and hold units(50) respectively and outputs the data. A first switch unit(30) stores the analog data generated from the analog signal input unit on a predetermined condenser among the analog data storage unit(20). A control unit(40) appoints the plurality of processing units of the decoding unit(10) sequentially according to a first clock signal inputted from the outside and stores the analog data generated from the analog signal input unit on the specific condenser of the analog data storage unit(20) sequentially by controlling the first switch unit(30).