| 摘要 |
A test mode circuit of a semiconductor device is provided to reduce layout area by reducing the number of test lines through a decoding operation. A test mode block(110) generates test mode signals by decoding addresses and a mode register set signal. A test signal generation part(120) generates test signals by decoding the test mode signals and then transfers the test signals to test target circuits(130). The number of first transmission lines for transmitting the test mode signals to the test mode block is smaller than the number of second transmission lines for transmitting the test signals to the test target circuits, and the length of the first transmission line is longer than the second transmission line.
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