发明名称 Latency Adjustment Between Integrated Circuit Chips
摘要 In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.
申请公布号 US2007045789(A1) 申请公布日期 2007.03.01
申请号 US20060553532 申请日期 2006.10.27
申请人 MENTOR GRAPHICS (HOLDINGS) LTD. 发明人 CLAVEQUIN JEAN-PAUL;COUTEAUX PASCAL;DIEHL PHILIPPE
分类号 H01L23/495;G06F1/10;G06F1/12 主分类号 H01L23/495
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