| 摘要 |
PROBLEM TO BE SOLVED: To provide a power source voltage distribution simulation method for a semiconductor integrated circuit, allowing reduction of a power unit model creation time, and allowing high-accuracy simulation considering variation of a floor plan. SOLUTION: In a step S1, design information (a core size CS, a coring width CW, a block shape BS, a macro shape MS, a block current BI, and a macro current MI or the like) is input to a simulator. In a step S2, information (a block position BP, a macro position MP, and a power source I/O position IOP) related to the floor plan is input to the simulator by a designer. In a step S3, power unit management table initialization, resistance modeling, and current source modeling are performed. In a step S5 (Figure), a static IR drop is calculated by use of a power unit management table CT obtained in a step S4. COPYRIGHT: (C)2007,JPO&INPIT
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