发明名称 WAFER EDGE PATTERNING IN SEMICONDUCTOR STRUCTURE FABRICATION
摘要 A lithographic process including providing a first wafer including (i) a first substrate, (ii) a first underlying layer on the first substrate, and (iii) a first resist layer on the first underlying layer; exposing a first plurality of full exposure fields of a first top resist layer plane through a product reticle, wherein the first top resist layer plane comprises a first top resist layer surface of the first resist layer, and wherein each full exposure field of the first plurality of full exposure fields is completely within the first top resist layer surface; and exposing a first plurality of partial exposure fields of the first top resist layer plane through a dummy reticle different from the product reticle, wherein each partial exposure field of the first plurality of partial exposure fields is partially but not totally within the first top resist layer surface.
申请公布号 US2007048668(A1) 申请公布日期 2007.03.01
申请号 US20050162006 申请日期 2005.08.25
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LIEGL BERNHARD R.
分类号 G03F7/20 主分类号 G03F7/20
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