发明名称 PLUG FABRICATING METHOD FOR DIELECTRIC LAYER
摘要 A method of fabricating a plug for a hole in a dielectric layer is disclosed. The method includes a first deposition process to partially filling the hole with a conductive material. Later, an etching process is performed at the partially filled hole. In addition, a second deposition process is performed to partially fill the hole with the conductive material again. Finally, the above steps are repeated until the hole is completely filled. The first deposition process and the second deposition process are done using a CVD or a PVD process. In addition, the etching process is done using halogen-containing gas.
申请公布号 US2007049017(A1) 申请公布日期 2007.03.01
申请号 US20050162088 申请日期 2005.08.29
申请人 HSIEH CHAO-CHING 发明人 HSIEH CHAO-CHING
分类号 H01L21/44 主分类号 H01L21/44
代理机构 代理人
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