| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To solve the problem in the prior art multilayer ceramic substrate that a misalignment between stacked layers upon lamination thereof or a difference in shrinkage behavior therebetween causes degradation of a connection reliability, because an electronic component built therein and wiring conductors previously formed in the multilayer substrate are connected either with one of upper and lower sides of the electronic component at a manufacturing stage. <P>SOLUTION: A multilayer substrate 10 having chip type electronic components built therein contains a multilayered substrate 11 of a plurality of stacked dielectric layers 11A having internally formed conductor pattern 12; and chip type electronic components 13 which are provided at the interface between the adjacent upper and lower dielectric layers 11A, and which each have external terminal electrodes 13A. The external terminal electrodes 13A are connected to an internal conductor pattern 12 via both of first and second connection conductors 14A and 14B, the first connection conductor 14A is extended along the chip type electronic component 13 in a direction downward from the interface, and the second connection conductor 14B is extended along the chip type electronic component 13 in a direction upward from the interface. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
