发明名称 METHOD AND STRUCTURE FOR POWER SEMICONDUCTOR PACKAGING
摘要 <P>PROBLEM TO BE SOLVED: To provide a semiconductor chip packaging structure including a dielectric film 10 having one or more through holes 11 aligned with one or more of contact pads 22 and 23 of at least one power semiconductor chip 21. <P>SOLUTION: A conductive layer 40 patterned next to the dielectric film 10 includes a plurality of conductive struts 41 which extend through the one or more through holes 11 aligned with the contact pads 22 and 23 and electrically connect the conductive layer 40 to the contact pads 22 and 23. In some embodiments, one or more gaps 91 can be formed between the dielectric film 10 and an active surface 24 of at least one power semiconductor chip 21. A method of fabricating the semiconductor chip packaging structure is also disclosed. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007053379(A) 申请公布日期 2007.03.01
申请号 JP20060221746 申请日期 2006.08.16
申请人 GENERAL ELECTRIC CO <GE> 发明人 FILLION RAYMOND A;BEAUPRE RICHARD A;ELASSER AHMED;WOJNAROWSKI ROBERT J;KORMAN CHARLES STEVEN
分类号 H01L25/07;H01L25/18 主分类号 H01L25/07
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