JUNCTION LEAKAGE SUPPRESSION IN NON-VOLATILE MEMORY DEVICES BY IMPLANTING PHOSPHOROUS AND ARSENIC INTO SOURCE AND DRAIN REGIONS

摘要

A memory device (100) includes a substrate (110) and source and drain regions (420, 430) formed in the substrate (110). The source and drain regions (420, 430) include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device (100) also includes a first dielectric layer (210) formed over the substrate (110) and a charge storage element (220) formed over the first dielectric layer (210). The memory device (100) may further include a second dielectric layer (230) formed over the charge storage element (220) and a control gate (240) formed over the second dielectric layer (230).