发明名称 |
Dual silicide semiconductor fabrication process |
摘要 |
A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.
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申请公布号 |
US2007048985(A1) |
申请公布日期 |
2007.03.01 |
申请号 |
US20050213470 |
申请日期 |
2005.08.26 |
申请人 |
JAWARANI DHARMESH;FU CHONG-CHENG;HALL MARK D |
发明人 |
JAWARANI DHARMESH;FU CHONG-CHENG;HALL MARK D. |
分类号 |
H01L21/28 |
主分类号 |
H01L21/28 |
代理机构 |
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