| 摘要 |
A processing device, comprising a processor; low power nonvolatile memory that communicates with said processor; and high power nonvolatile memory that communicates with said processor, wherein said processing device manages data using a cache hierarchy comprising a high power (HP) nonvolatile memory level for data in said high power nonvolatile memory and a low power (LP) nonvolatile memory level for data in said low power nonvolatile memory, wherein said LP nonvolatile memory level has a higher level in said cache hierarchy than said HP nonvolatile memory level. |
