| 摘要 |
A variable delay circuit (13, 27-30) is provided for delaying an input signal by a selectable variable time delay. The circuit comprises a selecting arrangement (21) for selecting how many of a first group (13) of delay elements (20) are connected in series for delaying an input signal. Identical delay elements (26) are connected in series to form a second group. A measuring circuit (27) repeatedly measures the delay provided by the second group, for example providing output pulses (IP) whose width or duration is equal to the delay. A reference pulse generator (29, 30) generates a series of reference pulses (IR), each of which is of a predetermined duration. A control circuit, such as a charge pump and integrator (28), compares the measurement pulses (IP) and the reference pulses (IR) to generate an error signal which is fed back to timing delay control inputs of all of the delay elements (20) such that the widths of the measurement and reference pulses (IP, IR) are made substantially equal to each other. Has uses in optical disk writers and tuners. |
