发明名称 Error detecting code calculation circuit, error detecting code calculation method, and recording apparatus
摘要 <p>The recording apparatus adds EDC to user data and transfers the EDC-added data to the scrambler in a sequence different from the coding direction Q. Though the processing data is added at an end in the direction Q, it is inserted at middle in the different sequence. Therefore, in order to transfer the EDC-added data in the different sequence, the EDC generator calculates an EDC intermediate value from an expected value of a latter part of an even number sector. Then, the EDC generator receives the user data in the different sequence and calculates EDC from expected values of the first half of the even number sector and an odd number sector and the EDC intermediate value. The expected value is an error detecting value of code string that has the same number of bits as the EDC-added data and a corresponding bit in the sequence of the direction Q is 1 and other bits are 0. </p>
申请公布号 EP1750264(A3) 申请公布日期 2007.02.28
申请号 EP20060015074 申请日期 2006.07.19
申请人 NEC ELECTRONICS CORPORATION 发明人 ARIYAMA, TAKEO
分类号 G11B20/18;H03M5/14;H03M13/09;H03M13/11 主分类号 G11B20/18
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