发明名称 |
Method of reducing the pattern effect in the CMP process |
摘要 |
A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.
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申请公布号 |
US7183199(B2) |
申请公布日期 |
2007.02.27 |
申请号 |
US20030724201 |
申请日期 |
2003.12.01 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
LIU CHI-WEN;TSAO JUNG-CHIH;FENG SHIEN-PING;CHEN KEI-WEI;LIN SHIH-CHI;CHUANG RAY |
分类号 |
H01L21/4763;H01L21/302;H01L21/321;H01L21/44;H01L21/768 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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