发明名称 |
Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof |
摘要 |
A delay locked loop (DLL) circuit having a duty cycle corrector (DCC) that has a broad range of duty cycle correction, consumes only a small amount of power, has few restrictions on operating frequency, and improves the characteristics of a memory device is described. The delay locked loop circuit includes an additional loop for duty cycle correction as well as loops for controlling a rising edge and a falling edge of output signals. Thus, the delay locked loop circuit can internally correct the duty cycle without the use of a phase blender.
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申请公布号 |
US7184509(B2) |
申请公布日期 |
2007.02.27 |
申请号 |
US20030619821 |
申请日期 |
2003.07.14 |
申请人 |
SAMSUNG ELCTRONICS CO., LTD. |
发明人 |
CHO GEUN-HEE;KIM KYU-HYOUN |
分类号 |
G06F1/04;H03D3/24;G11C11/407;H03K5/04;H03K5/13;H03K5/156;H03L7/06;H03L7/08;H03L7/081;H03L7/089;H04L7/033 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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