发明名称 |
Processor isolation technique for integrated multi-processor systems |
摘要 |
A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.
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申请公布号 |
US7185224(B1) |
申请公布日期 |
2007.02.27 |
申请号 |
US20030731971 |
申请日期 |
2003.12.10 |
申请人 |
CISCO TECHNOLOGY, INC. |
发明人 |
FREDENBURG WILLIAM;KEY KENNETH MICHAEL;WRIGHT MICHAEL L.;MARSHALL JOHN WILLIAM |
分类号 |
G06F11/00;G06F11/27 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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