发明名称 Memory system and method using ECC to achieve low power refresh
摘要 Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndromes are generated and stored. When transitioning from the reduced power refresh mode, data from the rows of memory cells are read, and the stored syndromes are used to determine if there are errors in the read data. The syndromes are also used to correct any errors that are found, and the corrected data are written to the rows of memory cells. By correcting any errors that exist when transitioning from the reduced power refresh mode, it is not necessary to use the syndromes to detect and correct errors while operating in the reduced power refresh mode.
申请公布号 US7184352(B2) 申请公布日期 2007.02.27
申请号 US20050192971 申请日期 2005.07.28
申请人 MICRON TECHNOLOGY, INC. 发明人 KLEIN DEAN A.;SCHRECK JOHN
分类号 G11C7/00;G06F11/10;G11C11/406 主分类号 G11C7/00
代理机构 代理人
主权项
地址