发明名称 |
Methods to facilitate etch uniformity and selectivity |
摘要 |
A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.
|
申请公布号 |
US2007042599(A1) |
申请公布日期 |
2007.02.22 |
申请号 |
US20050207493 |
申请日期 |
2005.08.19 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
TSUI TING Y.;JACQUES JEANNETTE M.;KRAFT ROBERT;JIANG PING |
分类号 |
H01L21/4763 |
主分类号 |
H01L21/4763 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|