| 摘要 |
<p>A phase splitter is provided to minimize skew among a plurality of clock signals as to PVT(Process, Voltage and Temperature) variation, by generating the plurality of clock signals by splitting one input clock signal. In a phase splitter(401) inputting an external clock signal and generating first and second internal clock signals, a first buffer(431) buffers the external clock signal. An inversion part(421) inverts the external clock signal. A second buffer(441) buffers an output signal of the inversion part. A first interpolation signal generation part(451) inverts the external clock signal. A second interpolation signal generation part(461) inverts the output signal of the inversion part. The first internal clock signal is generated by interpolating a signal outputted from the first buffer and a signal outputted from the second interpolation signal generation part. The second internal clock signal is generated by interpolating a signal outputted from the second buffer and a signal outputted from the first interpolation signal generation part.</p> |
