| 摘要 |
A memory element having a first and second logic components, each having a first input, a second input, and an output. The first input of each of the logic components is connected to the output of the other logic component. The second inputs of each of the logic components are connected to a control line. The first and second logic components are embodied such that when a control signal having a first level is applied to the control line at the respective output, a signal is output which has an output level that is inverted with respect to the level of the signal present at the respective first input, and when a control signal having a second level is applied to the control line at the respective output, a signal is output which has a predetermined level independent of the level of the signal present at the respective first input.
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