CMOS SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING THE OCCURRENCE OF LATCH-UP

摘要

A CMOS device is provided to avoid generation of latch-up caused by a parasitic PNP bipolar junction transistor and a parasitic NPN bipolar junction transistor by capturing holes or electrons generated on a boundary of an N-type well and a P-type well while using a parasitic bipolar junction transistor generated by an additionally formed impurity diffusion region. A first MOS transistor(240) is included in a first well. A second well(220) is formed in the first well, including a second MOS transistor(230) and an impurity diffusion region(270) of first conductivity type connected to a first voltage(VSS). An impurity diffusion region of first conductivity type that is included in the second MOS transistor, the second well, and an impurity diffusion region of first conductivity type connected to a first voltage constitute a parasitic bipolar junction transistor, so that the generation of latch-up is avoided by the operation of the parasitic bipolar junction transistors(Q1,Q2) formed in a CMOS semiconductor device(200). The first well further includes an impurity diffusion region of first conductivity type connected to the first voltage. The second well further includes an impurity diffusion region of second conductivity type connected to a second voltage(VDD).