发明名称 Method for estimating voltage droop on an ASIC
摘要 A simulation circuit model for a region of interest in an integrated circuit chip design is constructed that has a number of tiled, substantially identical sub-region simulation circuit models, each representing the supply voltage (V<SUB>DD</SUB>) distribution network in one of a number of corresponding sub-regions of the region. This mosaic of sub-region simulation circuit models is provided to an electronic simulator tool such as SPICE so that supply voltage properties in a selected one of the sub-regions can be analyzed.
申请公布号 US2007044063(A1) 申请公布日期 2007.02.22
申请号 US20050208678 申请日期 2005.08.22
申请人 FAOUR FOUAD A 发明人 FAOUR FOUAD A.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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