| 摘要 |
A digital frequency divider divides an input signal by a factor value specified as an N+1 bit value, utilizing a plurality of counter having a total of N bits. A single count value is generated based on a number of cycles of the input signal and a single generated count value compared with the factor value to generate a match signal comprising a pipelined match signal. The comparison may be performed utilizing a pipelined count value. An output signal from the digital frequency divider is toggled utilizing the match signal. The digital frequency dividing is performed utilizing at least one comparator and one counter for handling lower-order bits, and at least one comparator and one counter for handling higher-order bits. One bit of the factor value, and the output signal, is utilized to select one of two clock signals, which may be utilized to toggle the output signal.
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