发明名称 Memory control apparatus executing prefetch instruction
摘要 A memory controller reads data from DRAM at a request from a plurality of masters. It includes a prefetch buffer for storing a result of a pre-reading operation, and a register for setting a specific master among a plurality of masters. When a master requests a read, the memory controller pre-reads data subsequent to the requested data, and determines whether or not the master is a specific master set by the register. If the master is the specific master set by the register, then the result of the pre-read is stored in the prefetch buffer. Thus, the prefetch buffer can effectively function in a system having a plurality of masters.
申请公布号 US2007043910(A1) 申请公布日期 2007.02.22
申请号 US20060585210 申请日期 2006.10.24
申请人 CANON KABUSHIKI KAISHA 发明人 MINAMI TOSHIAKI
分类号 G06F12/00;G06F12/02;G06F13/16 主分类号 G06F12/00
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