| 摘要 |
Methods and systems for generating a signal are disclosed herein and may comprise digitally frequency dividing a input signal by a factor value specified as an N+1-bit value, utilizing a counter of N bits. A count value may be generated based on a number of cycles of the input signal and a generated count value compared with the factor value to generate a match signal comprising a pipelined match signal. The comparison may be performed utilizing a pipelined count value. An output signal from the digitally frequency dividing may be toggled utilizing the match signal. The digital frequency dividing may be performed utilizing a single comparator and may be performed utilizing a single counter. One of two clock signals may be selected and utilized to toggle the output signal. One bit of the factor value, and the output signal, may be utilized to select one of two clock signals.
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