发明名称 |
TEST SEQUENCE OPTIMIZATION METHOD AND DESIGN TOOL |
摘要 |
A method for defining a sequence of tests for testing a plurality of electronic devices including integrated circuits is disclosed. A reference group of devices is defined (110), after which the devices in said group are subjected to all available tests under consideration (120). For each test, the test results are collected, from which a fault coverage metric of the test for the group of devices is extracted (130). Next, a test benefit is calculated for each test (140), which is a ratio between the fault coverage metric and the test duration of said test. The test sequence is built by repeatedly adding tests to the sequence on the basis of their test benefits (160) until the overall fault coverage of the test sequence has reached a predefined threshold (170). Consequently, a test sequence that is optimized in terms of test cost is obtained. |
申请公布号 |
WO2007020602(A2) |
申请公布日期 |
2007.02.22 |
申请号 |
WO2006IB52849 |
申请日期 |
2006.08.17 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;VANDEWIELE, BERTRAND, J., L.;KRISHNAN, SHAJI |
发明人 |
VANDEWIELE, BERTRAND, J., L.;KRISHNAN, SHAJI |
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