| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a page buffer circuit in which a program time can be reduced by programming simultaneously dual pages. <P>SOLUTION: The page buffer circuit connected respectively to first bit lines connected to memory cells of a first memory cell block and second bit lines connected to memory cells of a second memory cell block is provided with a first bit line selecting circuit, a second bit line selecting circuit, a sensing circuit, a latch circuit latching sensing data or input data, a program control circuit outputting input data received from the latch circuit to a first bit line or a second bit line connected to a sensing node, and a verification circuit generating verification data in response to the sensing data received from a verification control signal and the latch circuit, when the first bit line selecting circuit connects any of the first bit lines to the sensing node, the second bit line selecting circuit separates the all second bit lines from the sensing node. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
