发明名称 POWER CONSUMPTION REDUCING METHOD AND LOGICAL DEVICE AND SYSTEM IN CACHE
摘要 PROBLEM TO BE SOLVED: To reduce power consumption in a memory system. SOLUTION: This method for reducing power consumption at a cache includes determining a nonuniform architecture for a cache for preparing the optimum number of caches for each cache set in the cache. The nonuniform architecture allows cache sets in the cache to have associativity values that differ from each other. The method also includes implementing the nonuniform architecture in the cache to reduce power consumption at the cache. The method also includes determining a code placement according to which code is writable to a memory separate from the cache. The code placement reduces the occurrences of inter cache-line sequential flows when the code is loaded from the memory to the cache. The method also includes compiling the code according to the code placement and writing the code to the memory for subsequent loading from the memory to the cache according to the code placement to further reduce power consumption at the cache. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007048285(A) 申请公布日期 2007.02.22
申请号 JP20060210350 申请日期 2006.08.01
申请人 FUJITSU LTD 发明人 ISHIHARA TORU;FALLAH FARZAN
分类号 G06F12/08 主分类号 G06F12/08
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