发明名称 ULTRASCALABLE VERTICAL MOS TRANSISTOR WITH PLANAR CONTACTS
摘要 A doped silicon block or island, formed above a drain electrode (17) in substrate (11) of a die or chip, has a height corresponding to the desired length of a channel (21, 23, 25). A source electrode (27) is formed above the silicon island and allows for contact (41) from above. Contact (43) from above may also be made with an L-shaped control gate (33, 35) and with the subsurface drain. A horizontal array of contacts for source, gate and drain is formed for the vertical transistor that is built. If nanocrystals (31) are incorporated into a layer (29) between the gate and the channel, a non-volatile floating gate transistor may be formed. Without the layer of nanocrystals, an MOS or CMOS transistor is formed.
申请公布号 WO2006121566(A3) 申请公布日期 2007.02.22
申请号 WO2006US13799 申请日期 2006.04.12
申请人 ATMEL CORPORATION;LOJEK, BOHUMIL 发明人 LOJEK, BOHUMIL
分类号 H01L29/94;H01L21/8238 主分类号 H01L29/94
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