发明名称 |
Vertical transistor trench capacitor DRAM with SOI logic devices |
摘要 |
A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions (24) and logic devices are formed in silicon-on-insulator ("SOI") regions (26) and where buried, doped glass to smooth the 250 nm step at the edge of the DRAM array region, making it easier to perform the lithography used to pattern the deep trenches (32) for storage in the bulk region. The resulting structure is also disclosed. |
申请公布号 |
EP1199745(A3) |
申请公布日期 |
2007.02.21 |
申请号 |
EP20010308539 |
申请日期 |
2001.10.05 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ADKISSON, JAMES A.;DIVAKARUNI, RAMACHANDRA;GAMBINO, JEFFREY P.;MANDELMAN, JACK A. |
分类号 |
H01L21/8242;H01L27/10;H01L21/84;H01L27/108;H01L27/12 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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