<p>A semiconductor device having high withstand voltage is provided. An active groove 22a is configured to include an elongate main groove part 26 and a sub groove part 27 connected to a side surface of the main groove part in the longitudinal direction, and a buried region 24 of a second conductivity type whose height is lower than the bottom of a base diffusion region 32a of the second conductivity type is provided on the bottom of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is in contact with the base diffusion region 32a through the active groove filling region 25. Since a single gate groove 83 is formed by the part above the buried region 24 in the single active groove 22a, the gate electrode plugs 48 are not separated, and this allows the electrode pattern to be simplified.</p>
