| 摘要 |
<p>A chip ( 1 ) has a substrate ( 2 ), an integrated circuit ( 3 ) provided on the substrate ( 2 ), a plurality of conductor zones (ME 1 , ME 2 , ME 3 , ME 4 , ME 5 ) and a passivating layer ( 5 ) provided to protect the conductor zones and the integrated circuit, through-holes ( 6, 7 ) being provided in the passivating layer ( 5 ) through which chip contacts ( 8, 9 ) are accessible, wherein additional chip contacts ( 10, 11 ) and connecting conductors ( 12, 13 ) are provided on the passivating layer ( 5 ) and wherein each additional chip contact has an electrically conductive connection to a chip contact via a connecting conductor.</p> |
