发明名称 |
Method for four direction low capacitance ESD protection |
摘要 |
The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device and its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.
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申请公布号 |
US7179691(B1) |
申请公布日期 |
2007.02.20 |
申请号 |
US20020207545 |
申请日期 |
2002.07.29 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
LEE JIAN-HSING;CHEN SHUI HUN YI |
分类号 |
H01L21/332;H01L21/331 |
主分类号 |
H01L21/332 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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