发明名称 |
Network synchronization architecture for a Broadband Loop Carrier (BLC) system |
摘要 |
A combined wide area network (WAN) port/synchronization unit that receives inputs including data and timing information and that synchronizes the data for transmission. The unit includes the following components. A network interface receives the input and removes data and primary timing information from the input. A data-path function processes the data. A reference selection unit receives timing information from the network interface as well as timing information from a secondary combined WAN port/synchronization unit. A synchronization control unit selects the most reliable timing information from the plurality of timing information inputs to the reference selection unit. A multiplexor multiplexes the timing information with the processed data across a link.
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申请公布号 |
US7181545(B2) |
申请公布日期 |
2007.02.20 |
申请号 |
US20030356336 |
申请日期 |
2003.01.31 |
申请人 |
CIENA CORP. |
发明人 |
DZIAWA MICHAEL;GAZIER MICHAEL |
分类号 |
G06F15/16;H01M8/02;H04J3/06 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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