发明名称 DRAM cell structure with tunnel barrier
摘要 The invention relates to a transistor that is provided with a first source/drain area (S/D 1 ), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2 ) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D 1 ). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D 1 ) are arranged in the insulating area. The second source/drain area (S/D 2 ) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.
申请公布号 US7180115(B1) 申请公布日期 2007.02.20
申请号 US20000130441 申请日期 2000.11.14
申请人 INFINEON TECHNOLOGIES AG 发明人 HOFMANN FRANZ;ROESNER WOLFGANG;RISCH LOTHAR;SCHLOESSER TILL
分类号 H01L27/108;H01L21/336;H01L21/8242;H01L27/12;H01L29/78;H01L29/786 主分类号 H01L27/108
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