Semiconductor memory device including 4TSRAMs

摘要

Disclosed is a method of improving stability of a memory cell in read mode in an SRAM including a memory cell comprising two access MOS transistors and two drive MOS transistors. The magnitude of voltage between gate and source of an access transistor of a memory cell connected to a selected word line is controlled to be smaller than a power-supply voltage by controlling the voltage of selected word line WL in read mode.