发明名称 |
Frequency multiplier capable of adjusting duty cycle of a clock and method used therein |
摘要 |
Provided is a frequency multiplier including a delay circuit, an XOR gate, and a control circuit and a method of operating such a frequency multiplier to adjust the duty cycle of a clock signal. During operation of the frequency multiplier the delay circuit receives a first clock signal and generates a delayed clock signal. The XOR gate receives the first clock signal and the delayed clock signal, performs an XOR operation on the received signals and outputs a second clock signal that has a frequency that is a multiple of the first clock signal. The control circuit monitors the phase difference between the first clock signal and the delayed clock signal and outputs a control signal corresponding to the detected phase difference to the delay circuit to adjust the time delay applied to the first clock signal by the delay circuit.
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申请公布号 |
US7180340(B2) |
申请公布日期 |
2007.02.20 |
申请号 |
US20030655024 |
申请日期 |
2003.09.05 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JUNG GUN-OK;PARK SUNG-BAE |
分类号 |
G06F1/06;H03B19/00;G01R25/04;G06F7/68;G11C11/407;H03K5/00;H03K5/04;H03K5/13;H03K5/14;H03K5/156;H03L7/081 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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