发明名称 |
Parallel layer 2 and layer 3 processing components in a network router |
摘要 |
A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When both the L2 and L3 generation units complete their operations for a particular packet, a build component combines the generated L2 and L3 header information from the buffers to form a complete packet header.
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申请公布号 |
US7180893(B1) |
申请公布日期 |
2007.02.20 |
申请号 |
US20020102960 |
申请日期 |
2002.03.22 |
申请人 |
JUNIPER NETWORKS, INC. |
发明人 |
SINDHU PRADEEP;LIM RAYMOND M.;LIBBY JEFFREY G. |
分类号 |
H04L12/56;G06F9/30;H04J3/22 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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