发明名称 Backward-compatible parallel DDR bus for use in host-daughtercard interface
摘要 A host-daughtercard interface is pin compatible with a legacy interface but redefines a subset of pins to implement a high-bandwidth double data-rate (DDR) bus. By inspecting a cookie on the daughtercard, the host platform determines whether the daughtercard supports the DDR bus or the legacy interface, and then configures the subset of pins to implement the legacy interface or the DDR bus.
申请公布号 US7181551(B2) 申请公布日期 2007.02.20
申请号 US20030688446 申请日期 2003.10.17
申请人 CISCO TECHNOLOGY, INC. 发明人 GRISHAW JAMES EVERETT;HENNIGER MICKEY RAMAL
分类号 G06F3/00;G06F13/00;H04L 主分类号 G06F3/00
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