发明名称 Integrated circuit free from accumulation of duty ratio errors
摘要 An integrated circuit includes a first signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input signal, followed by outputting the first input signal after logic inversion thereof in response to a first state of a switching signal and outputting the first input signal without logic inversion in response to a second state of the switching signal, a signal processing circuit which performs signal processing based on the output of the first signal-inversion switching circuit, and a second signal-inversion switching circuit which receives the output of the first signal-inversion switching circuit passing through the signal processing circuit as a second input signal, followed by outputting the second input signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input signal without logic inversion in response to the first state of the switching signal.
申请公布号 US7180512(B2) 申请公布日期 2007.02.20
申请号 US20030335925 申请日期 2003.01.03
申请人 FUJITSU LIMITED 发明人 KUMAGAI MASAO;FUKUDA HIDETO;UDO SHINYA
分类号 G02F1/133;G09G5/00;G09G3/20;G09G3/34;G09G3/36;G09G5/10 主分类号 G02F1/133
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