发明名称 ERROR DETECTING CODE CALCULATION CIRCUIT, ERROR DETECTING CODE CALCULATION METHOD, AND RECORDING DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce the amount of accesses to a data buffer when error detecting codes for detecting errors of user data are calculated. SOLUTION: This recording device 1 adds EDCs to user data, and transmits them to a scramble circuit in different order from a coding direction Q. Processing data is constituted so as to be last added in order of the direction Q, but constituted so as to be inserted intermediately in the different order. Accordingly, when data with the EDCs are transmitted in different order, first, a EDC generation section 31 calculates an EDC intermediate value from an expected value of a last half part of an even number sector, and secondly, the EDC generation section 34 receives the user data in the different order and calculates a EDC from an expected value of a first half part of the even number sector, and an expected value and an EDC intermediate value of an odd number sector. The expected value has the number of the same bits as the data with the EDCs, and is an error detection value of a code sequence in which only corresponding bits when the order of the direction Q is matched are set to 1, and others are set to 0. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007042234(A) 申请公布日期 2007.02.15
申请号 JP20050226705 申请日期 2005.08.04
申请人 NEC ELECTRONICS CORP 发明人 ARIYAMA TAKEO
分类号 G11B20/18;G11B20/10;G11B20/12 主分类号 G11B20/18
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