| 摘要 |
<p>A one time-programmable memory bitcell (9) comprises a transistor (13) and a fuse (12). The transistor is arranged to receive a first signal and, upon receipt of the first signal, to enable communication of a second signal to the fuse. Preferably, the input terminal of the transistor is connected to the source of the first signal, the output terminal of the transistor is connected to one terminal of the fuse the other terminal of the fuse is connected to the source of the second signal. The present invention also provides a fuse memory array and associated control circuit.</p> |
