NANOSCALE INTERCONNECTION INTERFACE

摘要

One embodiment of the present invention provides a demultiplexer implemented as a nonowire crossbar (3000) or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines (3003, 3004) to 2^k or fewer nanowires (3006-3009), employing supplemental, internal address lines (3010, 3012) to map 2^k nanowire addresses to a larger, internal, n-bit address space, where n > k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2^k nanowires, with n > k, using 2^k, well-distributed, n-bit external addresses to access the 2^k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire address to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.