| 摘要 |
Provided is a technique of optimizing a virtual operation timing of a processor after emulation. In order to accurately estimate the number of bus access cycles after the emulation, the number of cycles required for an access when an instruction is issued from a processor (MIPS) is divided for each of factors, and the number of bus access cycles is estimated as the sum of the numbers of cycles required for the respective factors. For example, a BusArbiter object receives data indicating a substantial time required for execution of a request from a peripheral that executes the request from the MIPS and a current status of a DMA from a DMA controller, and informs the MIPS of the received data and the received status. The MIPS optimizes its own virtual operation timing in accordance with the substantial time.
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