发明名称 SELECTIVE ACTIVATION OF ERROR MITIGATION BASED ON BIT LEVEL ERROR COUNT
摘要 Embodiments of apparatuses and methods for selective activation of error mitigation based on bit level error counts are disclosed. In one embodiment, an apparatus includes a plurality of state elements, an error counter, and activation logic. The error counter is to count the number of bit level errors in the state elements. The activation logic is to increase error mitigation if the number of bit level errors exceeds a threshold value.
申请公布号 WO2006135937(A3) 申请公布日期 2007.02.15
申请号 WO2006US23634 申请日期 2006.06.13
申请人 INTEL CORPORATION;BISWAS, ARIJIT;RAASSCH, STEVEN;MUKHERJEE, SHUBHENDU 发明人 BISWAS, ARIJIT;RAASSCH, STEVEN;MUKHERJEE, SHUBHENDU
分类号 G06F11/10 主分类号 G06F11/10
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