| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce power consumption at the time of random access in a memory cell array having a two transistor-one capacitor type memory cell as a base unit. <P>SOLUTION: Each memory cell MCaj (j=1 to 8) has a write transistor TW whose gate is connected to a write word line and whose source or drain is connected to a storage node SN, read transistor TR whose gate is connected to the storage node SN and a capacitor C connected between the storage node SN and a read word line and at least one of the write word line and the read word line is hierarchized. The hierarchized word line consists of a main word line MWLw or MWLr and a plurality of sub word lines SWLw, ... or SWLr, ... connected to the plurality of memory cells MCaj respectively arranged in the wiring direction of the main word line and the main word line and the sub word line are connected to each other via a switch 2w or 2r. <P>COPYRIGHT: (C)2007,JPO&INPIT |
