| 摘要 |
The invention relates to a circuit arrangement for producing a defined output signal in an CMOS integrated circuit. The aim of said invention is to develop a circuit arrangement which make it possible to carry out a robust largely independent of another circuit diagnosis of a VDD- or GND connection interruption, does not require the upper limit of a load resistance, does not limit the upper operation temperature of the integrated circuit and which can be embodied on a chip. For this purpose, the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit, the gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance, the second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS and the drain terminal of the second N channel depletion transistor is connected to a potential VDD. |
