| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To solve the problem that jitter or duty deterioration of N-mutiplied (N is a positive integer) clock may occur by varying a delay value of a delay circuit because of process variation in the prior art where the N-multiplied clock is generated by exclusively ORing N clocks delayed for a 1/2N term by the delay circuit. <P>SOLUTION: According to the present invention, a signal delayed for a 1/2N (N is a positive integer) term in advance is input from the outside, so that delay of a delay circuit is not varied by variation of semiconductor manufacturing processes. Therefore, jitter or duty deterioration can be reduced for an N-multiplied clock generated by exclusive OR, so that a high-precision N-multiplied clock can be generated. Furthermore, the N-multiplied clock is output outside a semiconductor integrated circuit, frequency dispersion or duty deterioration is computed and an input timing and a duty of the input signal are adjusted, thereby supplying a high-precision N-multiplied clock. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
