| 摘要 |
PROBLEM TO BE SOLVED: To reduce the connection resistance between internal electrode layers in the stacking direction via a through-hole without reducing the area of individual internal electrode layers while keeping a low ESL (equivalent series inductance). SOLUTION: The multilayered capacitor 2 is such that a plurality of first planar internal electrode layers 6 and a plurality of second planar internal electrode layers 8 are alternately stacked via dielectric layers in the main body 10 made by stacking the dielectric layers 4. First external electrodes 12 and second external electrodes 14 are arranged only on the first end face 10a of the main body 10. The internal electrode layers 6 and 8 stacked near the first end face 10a of the main body 10 and the external electrodes 12 and 14 are connected to each other by pillar-shaped electrodes 16 and 18 for extraction. The internal electrode layers 6 and 8 stacked inside the main body 10 are connected to each other by pillar-shaped electrodes 20 and 22 for interlayer connection. The pillar-shaped electrodes 20 and 22 for interlayer connection have a larger cross-sectional area than that of the pillar-shaped electrodes 16 and 18 for extraction. COPYRIGHT: (C)2007,JPO&INPIT
|
