| 摘要 |
<p>The present invention relates to a method for synthesizing digital clock signals for an electronic device under test (DUT) having a plurality of pins, said method comprising the steps of generating centrally a reference clock (RCLK), and distributing said reference clock (RCLK) to a number of electronic circuits, each of said electronic circuits comprising a test signal processor (20a,20b,20c) controlling electrically said pins of said device under test (DUT) with predetermined signal patterns, and synthesizing locally at said test signal processor (20a,20b,20c) a digital clock signal (PCLK), said digital clock signal (PCLK) being individual for said pin of said device under test (DUT) electrically controlled by said test signal processor (20a,20b,20c), where
said synthesizing comprises a division of said reference clock (RCLK) by M and a multiplication of the divided reference clock by N avg within a phase locked loop, wherein N avg and M integer with N avg < M,
charactrized in that
said N avg /M divided reference clock (RCLK) is synchronized with a synchronizing signal (SYNC) generated centrally wherein the generation of said synchronizing signal (SYNC) comprises a division of said reference clock (RCLK) by M and a multiplication of the divided reference clock by N within a phase locked loop, wherein N and M are integer with N < M, and in that said synchronizing signal (SYNC) is distributed to said electronic circuits.</p> |
